Our client is the worldwide leader in digital entertainment products. Their mission is to expand its leadership role in the lifestyle Personal Digital Entertainment market, using groundbreaking technology and leading-edge designs for not just the technically-savvy consumers, but for everyone who enjoys entertainment. With strong focus on user-friendly interface, multiple features and cool industrial designs, our client brand is synonymous with lifestyle Personal Digital Entertainment.

Our client’s global corporate headquarters is located in Singapore, in the heart of the Asia-Pacific region. It has regional headquarters in the US (Milpitas, California), Europe (Dublin, Ireland) and Asia (Singapore).

RESPONSIBILITIES:

The incumbent will support our Singapore IC Design Centre and will be responsible for IP integration and verification. This will include RTL coding and functional verification, block level design specification and
design review. You will also be in charge of the functional test plan, maintaining and improving the test harness as well as FPGA prototyping and back annotated simulation debugging.

REQUIREMENTS:

• Degree in Electronic Engineering or its equivalent
• Minimum 2 years experience in RTL coding (VHDL or verilog)
• Relevant experience in RTL, gatelevel debug/ verification and in using Mentor Modelsim/ Questa simulator
• Knowledge of FPGA, synthesis and STA will be an added advantage
• Possess scripting skills, preferably Perl/ TCL

The following information should be included in the resume:

• Date of availability
• Detailed job scope & skills
• Current and last drawn salary of last job
• Reason for leaving past 3 jobs
• Salary expectation
• Recent passport photo

Thank you for your interest. Please send your CV in MS Words Format ONLY to asic@hrx.sg for faster processing.

Desiree Tan (R1218716)